The electrostatic protection design of an integrated circuit chip is one of necessary conditions for ensuring the reliable work of the chip. The electronic static impact occurs everywhere in life. Along with the continuous development of integrated circuit technology era, the sizes of devices constituting a circuit becomes smaller and smaller. Since the electrostatic impact itself has the features of short time and very large instantaneous current, in the case that the size of a device is small, the electrostatic impact will form a vast equivalent electric field inside the device and directly break through the device, so that the device suffers irreversible physical damage and breaks down.
The purpose of the ESD protection strategy is to provide a low-resistance discharge channel for a large amount of charge brought about by the impact when electrostatic impact occurs. The electrostatic charge is discharged from the low-resistance discharge channel so as to avoid the damage to inside logical circuits. Along with the improvement of technologies, the threat caused by the electrostatic impact to logical circuits of a chip becomes bigger and bigger, and the significance of an effective anti-electrostatic impact protection design scheme becomes more and more prominent correspondingly.
There are many factors required to be considered for the chip ESD impact protection design. The discharge performance of a discharge device can be optimized from the device level; and an effective discharge device trigger mechanism can be designed from the circuit level, which can allow a discharge device to be effectively turned on when impact occurs and strictly shutoff during normal power-up. Certainly, along with the rising and development of power integrated circuits, the electrostatic protection work of power devices also gains sufficient attention of researchers. The circuit shown in FIG. 1 is a schematic diagram of a known ESD protection circuit, in which the turn-on channel () and shutoff channel () of a discharge transistor () are separated. In this case, when impact occurs, the turn-on time of the discharge transistor mainly depends on the equivalent RC delay of the shutoff channel, allowing a margin for shrinking an ESD impact detection resistor and capacitor. On one hand, the shrinkage of passive resistor and capacitor can facilitate the saving of layout area, and on the other hand, the shrinkage of passive capacitor and resistor is an effective way for improving the circuit itself to prevent the false trigger during quick power-up. However, the resistor of the shutoff channel of the circuit shown in FIG. 1 is realized by a PMOS transistor of an active device, and in the integrated circuit technology, the resistor realized by an active device is difficult to achieve large resistance value generally. In order to make the detection capacitance resistance time constant (i.e. the product of C1 capacitance value and R1 resistance value) of the circuit shown in FIG. 1 actually small, the time delay of the discharge transistor shutoff channel under ESI) impact requires to be large enough, such that the passive capacitors C2 and C3 are correspondingly large, resulting in the great increase of the layout area of the chip in structure shown in FIG. 1.